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20.1.4 Use Cases
20.1.5 TIMER Registers
Table 20-10 lists the memory-mapped registers for the TIMER. All register offset addresses not listed in
Table 20-10 should be considered as reserved locations and the register contents should not be modified.
Table 20-10. TIMER REGISTERS
Offset Acronym Register Name Section
00h TIDR Identification Register Section 20.1.5.1
10h TIOCP_CFG Timer OCP Configuration Register Section 20.1.5.2
20h IRQ_EOI Timer IRQ End-of-Interrupt Register Section 20.1.5.3
24h IRQSTATUS_RAW Timer Status Raw Register Section 20.1.5.4
28h IRQSTATUS Timer Status Register Section 20.1.5.5
2Ch IRQENABLE_SET Timer Interrupt Enable Set Register Section 20.1.5.6
30h IRQENABLE_CLR Timer Interrupt Enable Clear Register Section 20.1.5.7
34h IRQWAKEEN Timer IRQ Wakeup Enable Register Section 20.1.5.8
38h TCLR Timer Control Register Section 20.1.5.9
3Ch TCRR Timer Counter Register Section 20.1.5.10
40h TLDR Timer Load Register Section 20.1.5.11
44h TTGR Timer Trigger Register Section 20.1.5.12
48h TWPS Timer Write Posting Bits Register Section 20.1.5.13
4Ch TMAR Timer Match Register Section 20.1.5.14
50h TCAR1 Timer Capture Register Section 20.1.5.15
54h TSICR Timer Synchronous Interface Control Register Section 20.1.5.16
58h TCAR2 Timer Capture Register Section 20.1.5.17
3566
Timers SPRUH73H–October 2011–Revised April 2013
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