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Enhanced Capture (eCAP) Module
15.3.4.1.1 TSCTR Register (offset = 0h) [reset = 0h]
TSCTR is shown in Figure 15-116 and described in Table 15-109.
Figure 15-116. TSCTR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSCTR
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 15-109. TSCTR Register Field Descriptions
Bit Field Type Reset Description
31-0 TSCTR R/W 0h
Active 32 bit counter register that is used as the capture time-base
1635
SPRUH73H–October 2011–Revised April 2013 Pulse-Width Modulation Subsystem (PWMSS)
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