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EDMA3 Registers
11.4.2.7.13 Destination FIFO Destination Address Register (DFDSTn)
The destination FIFO destination address register (DFDSTn) is shown in Figure 11-127 and described in
Table 11-112.
NOTE: The value for n varies from 0 to DSTREGDEPTH for the given EDMA3TC.
Figure 11-127. Destination FIFO Destination Address Register (DFDSTn)
31 16
DADDR
R-0
15 0
DADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 11-112. Destination FIFO Destination Address Register (DFDSTn) Field Descriptions
Bit Field Value Description
31-0 DADDR 0 Destination address for the destination FIFO register set. When a transfer request (TR) is complete, the
final value should be the address of the last write command issued.
11.4.2.7.14 Destination FIFO B-Index Register (DFBIDXn)
The destination FIFO B-index register (DFBIDXn) is shown in Figure 11-128 and described in Table 11-
113.
NOTE: The value for n varies from 0 to DSTREGDEPTH for the given EDMA3TC.
Figure 11-128. Destination FIFO B-Index Register (DFBIDXn)
31 16
DBIDX
R-0
15 0
SBIDX
R-0
LEGEND: R = Read only; -n = value after reset
Table 11-113. Destination FIFO B-Index Register (DFBIDXn) Field Descriptions
Bit Field Value Description
31-16 DBIDX 0-FFFFh B-Index offset between destination arrays. Represents the offset in bytes between the starting
address of each destination.
15-0 SBIDX 0 Always read as 0.
1015
SPRUH73H–October 2011–Revised April 2013 Enhanced Direct Memory Access (EDMA)
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