Enhanced Capture (eCAP) Module
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15.3.4.1.10 ECFLG Register (offset = 2Eh) [reset = 0h]
ECFLG is shown in Figure 15-125 and described in Table 15-118.
Figure 15-125. ECFLG Register
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
CMPEQ PRDEQ CNTOVF CEVT4 CEVT3 CEVT2 CEVT1 INT
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 15-118. ECFLG Register Field Descriptions
Bit Field Type Reset Description
15-8 Reserved R 0h
7 CMPEQ R 0h Compare Equal Compare Status Flag.
This flag is only active in APWM mode.
0x0 = Indicates no event occurred
0x1 = Indicates the counter (TSCTR) reached the compare register
value (ACMP)
6 PRDEQ R 0h Counter Equal Period Status Flag.
This flag is only active in APWM mode.
0x0 = Indicates no event occurred
0x1 = Indicates the counter (TSCTR) reached the period register
value (APRD) and was reset.
5 CNTOVF R 0h Counter Overflow Status Flag.
This flag is active in CAP and APWM mode.
0x0 = Indicates no event occurred.
0x1 = Indicates the counter (TSCTR) has made the transition from
0xFFFFFFFF to 0x00000000
4 CEVT4 R 0h
Capture Event 4 Status Flag This flag is only active in CAP mode.
0x0 = Indicates no event occurred
0x1 = Indicates the fourth event occurred at ECAPn pin
3 CEVT3 R 0h Capture Event 3 Status Flag.
This flag is active only in CAP mode.
0x0 = Indicates no event occurred.
0x1 = Indicates the third event occurred at ECAPn pin.
2 CEVT2 R 0h Capture Event 2 Status Flag.
This flag is only active in CAP mode.
0x0 = Indicates no event occurred.
0x1 = Indicates the second event occurred at ECAPn pin.
1 CEVT1 R 0h Capture Event 1 Status Flag.
This flag is only active in CAP mode.
0x0 = Indicates no event occurred.
0x1 = Indicates the first event occurred at ECAPn pin.
0 INT R 0h
Global Interrupt Status Flag
0x0 = Indicates no interrupt generated.
0x1 = Indicates that an interrupt was generated.
1646
Pulse-Width Modulation Subsystem (PWMSS) SPRUH73H–October 2011–Revised April 2013
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