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RTC_SS
20.3.5.19 RTC_OSC_REG Register (offset = 54h) [reset = 10h]
RTC_OSC_REG is shown in Figure 20-79 and described in Table 20-82.
Figure 20-79. RTC_OSC_REG Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved EN_32KCLK Reserved OSC32K_GZ SEL_32KCLK_SRC RES_SELECT SW2 SW1
R-0h R/W-0h R-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-82. RTC_OSC_REG Register Field Descriptions
Bit Field Type Reset Description
31-7 Reserved R 0h
6 EN_32KCLK R/W 0h
32-kHz clock enable post clock mux of rtc_32k_clk_rtc_32k_aux_clk
and rtc_32k_clk_rtc_32k_clk
0x0 = Disable
0x1 = Enable
5 Reserved R 0h
4 OSC32K_GZ R/W 1h
Disable the oscillator and apply high impedance to the output
0x0 = Enable
0x1 = Disabled and high impedance
3 SEL_32KCLK_SRC R/W 0h 32-kHz clock source select
0x0 = Selects internal clock source, namely
rtc_32k_clk_rtc_32k_aux_clk
0x1 = Selects external clock source, namely rtc_32k_clk_rtc_32k_clk
that is from the 32-kHz oscillator
2 RES_SELECT R/W 0h
External feedback resistor
0x0 = Internal
0x1 = External
1 SW2 R/W 0h
Inverter size adjustment
0 SW1 R/W 0h
Inverter size adjustment
3653
SPRUH73H–October 2011–Revised April 2013 Timers
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