Interrupt Controller Registers
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6.5.1.5 INTC_SIR_FIQ Register (offset = 44h) [reset = FFFFFF80h]
INTC_SIR_FIQ is shown in Figure 6-8 and described in Table 6-8.
This register supplies the currently active FIQ interrupt number
Figure 6-8. INTC_SIR_FIQ Register
31 30 29 28 27 26 25 24
SpuriousFIQ
R-1FFFFFFh
23 22 21 20 19 18 17 16
SpuriousFIQ
R-1FFFFFFh
15 14 13 12 11 10 9 8
SpuriousFIQ
R-1FFFFFFh
7 6 5 4 3 2 1 0
SpuriousFIQ ActiveFIQ
R-1FFFFFFh R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-8. INTC_SIR_FIQ Register Field Descriptions
Bit Field Type Reset Description
31-7 SpuriousFIQ R 1FFFFFFh
Spurious FIQ flag
6-0 ActiveFIQ R 0h
Active FIQ number
210
Interrupts SPRUH73H–October 2011–Revised April 2013
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