Interrupt Controller Registers
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6.5.1.41 INTC_ISR_CLEAR3 Register (offset = F4h) [reset = 0h]
INTC_ISR_CLEAR3 is shown in Figure 6-44 and described in Table 6-44.
This register is used to clear the software interrupt bits
Figure 6-44. INTC_ISR_CLEAR3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IsrClear
W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-44. INTC_ISR_CLEAR3 Register Field Descriptions
Bit Field Type Reset Description
31-0 IsrClear W 0h
Write 1 clears the sofware interrupt bits to 0, reads return 0
246
Interrupts SPRUH73H–October 2011–Revised April 2013
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