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I2C Registers
21.4.1.3 I2C_SYSC Register (offset = 10h) [reset = 0h]
I2C_SYSC is shown in Figure 21-18 and described in Table 21-11.
This register allows controlling various parameters of the peripheral interface.
Figure 21-18. I2C_SYSC Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved CLKACTIVITY
R-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved IDLEMODE ENAWAKEUP SRST AUTOIDLE
R-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 21-11. I2C_SYSC Register Field Descriptions
Bit Field Type Reset Description
31-10 Reserved R 0h
9-8 CLKACTIVITY R/W 0h Clock Activity selection bits.
Those bits (one bit for each clock signal present on the boundary of
the module) are set to 1 to disable external clock gating mechanism
in Idle Mode.
Values after reset are low (for both 2 bits).
Note: If the System (functional) Clock is cut-off, the module will
assert a WakeUp event when it asynchronously detects a Start
Condition on the I2C Bus.
Note that in this case the first transfer will not be taken into account
by the module (NACK will be detected by the external master).
0x0 = Both clocks can be cut off
0x1 = Only Interface/OCP clock must be kept active; system clock
can be cut off
0x2 = Only system clock must be kept active; Interface/OCP clock
can be cut off
0x3 = Both clocks must be kept active
7-5 Reserved R 0h
4-3 IDLEMODE R/W 0h Idle Mode selection bits.
These two bits are used to select one of the idle mode operation
mechanisms.
Value after reset is 00 (Force Idle).
0x1 = No Idle mode
0x2 = Smart Idle mode
0x3 = Smart-idle wakeup. Only available on I2C0.
2 ENAWAKEUP R/W 0h Enable Wakeup control bit.
When this bit is set to 1, the module enables its own wakeup
mechanism.
Value after reset is low.
0x0 = Wakeup mechanism is disabled
0x1 = Wakeup mechanism is enabled
3719
SPRUH73H–October 2011–Revised April 2013 I2C
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