CONTROL_MODULE Registers
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9.3.72 timer_evt_capt Register (offset = FD0h) [reset = 0h]
timer_evt_capt is shown in Figure 9-75 and described in Table 9-82.
Figure 9-75. timer_evt_capt Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved timer7_evtcapt
R-0h R/W-0h
15 14 13 12 11 10 9 8
Reserved timer6_evtcapt
R-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved timer5_evtcapt
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 9-82. timer_evt_capt Register Field Descriptions
Bit Field Type Reset Description
31-21 Reserved R 0h
20-16 timer7_evtcapt R/W 0h Timer 7 event capture mux
15-13 Reserved R 0h
12-8 timer6_evtcapt R/W 0h Timer 6 event capture mux
7-5 Reserved R 0h
4-0 timer5_evtcapt R/W 0h Timer 5 event capture mux
836
Control Module SPRUH73H–October 2011–Revised April 2013
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