Ethernet Subsystem Registers
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14.5.7.7 RX_PAUSE Register (offset = 18h) [reset = 0h]
RX_PAUSE is shown in Figure 14-179 and described in Table 14-195.
CPGMAC_SL RECEIVE PAUSE TIMER REGISTER
Figure 14-179. RX_PAUSE Register
31 30 29 28 27 26 25 24
rx_pausetimer
R-0h
23 22 21 20 19 18 17 16
rx_pausetimer
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-195. RX_PAUSE Register Field Descriptions
Bit Field Type Reset Description
31-16 rx_pausetimer R 0h RX Pause Timer Value - This field allows the contents of the receive
pause timer to be observed (and written in test mode).
The receive pause timer is loaded with 0xFF00 when the
CPGMAC_SL sends an outgoing pause frame (with pause time of
0xFFFF).
The receive pause timer is decremented at slot time intervals.
If the receive pause timer decrements to zero, then another outgoing
pause frame will be sent and the load/decrement process will be
repeated.
15-0 Reserved R 0h
1420
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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