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Power, Reset, and Clock Management
8.1.13.3.2 PM_WKUP_PWRSTCTRL Register (offset = 4h) [reset = 8h]
PM_WKUP_PWRSTCTRL is shown in Figure 8-173 and described in Table 8-190.
Controls power state of WKUP power domain
Figure 8-173. PM_WKUP_PWRSTCTRL Register
31 30 29 28 27 26 25 24
Reserved Reserved Reserved Reserved Reserved Reserved
R-0h R-0h R-0h R-0h R-0h R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved LowPowerStateChang LogicRETState Reserved Reserved
e
R-0h R/W-0h R/W-1h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-190. PM_WKUP_PWRSTCTRL Register Field Descriptions
Bit Field Type Reset Description
31-30 Reserved R 0h
29 Reserved R 0h
28 Reserved R 0h
27 Reserved R 0h
26-25 Reserved R 0h
24-5 Reserved R 0h
4 LowPowerStateChange R/W 0h Power state change request when domain has already performed a
sleep transition.
Allows going into deeper low power state without waking up the
power domain.
0x0 = DIS : Do not request a low power state change.
0x1 = EN : Request a low power state change. This bit is
automatically cleared when the power state is effectively changed or
when power state is ON.
3 LogicRETState R/W 1h
Logic state when power domain is RETENTION
0x0 = logic_off : Only retention registers are retained and remaing
logic is off when the domain is in RETENTION state.
0x1 = logic_ret : Whole logic is retained when domain is in
RETENTION state.
2 Reserved R 0h
1-0 Reserved R 0h
717
SPRUH73H–October 2011–Revised April 2013 Power, Reset, and Clock Management (PRCM)
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