UART Registers
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19.5.1.13 Line Status Register (LSR) - IrDA Mode
When the IrDA line status register (LSR) is read, LSR[4:2] reflect the error bits (FL, CRC, ABORT) of the
frame at the top of the status FIFO (next frame status to be read). The IrDA line status register (LSR) is
shown in Figure 19-46 and described in Table 19-42.
Figure 19-46. IrDA Line Status Register (LSR)
15 8
Reserved
R-0
7 6 5 4 3 2 1 0
THR_EMPTY STS_FIFO_FULL RX_LAST_BYTE FRAME_TOO_LONG ABORT CRC STS_FIFO_E RX_FIFO_E
R-1 R-0 R-1 R-0 R-0 R-0 R-1 R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-42. IrDA Line Status Register (LSR) Field Descriptions
Bit Field Value Description
15-8 Reserved 0 Reserved.
7 THR_EMPTY 0 Transmit holding register (TX FIFO) is not empty.
1 Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed.
6 STS_FIFO_FULL 0 Status FIFO is not full.
1 Status FIFO is full.
5 RX_LAST_BYTE 0 The RX FIFO (RHR) does not contain the last byte of the frame to be read.
1 The RX FIFO (RHR) contains the last byte of the frame to be read. This bit is set to 1 only
when the last byte of a frame is available to be read. It is used to determine the frame
boundary. It is cleared on a single read of the LSR register.
4 FRAME_TOO_LONG 0 No frame-too-long error in frame.
1 Frame-too-long error in the frame at the top of the status FIFO (next character to be read).
This bit is set to 1 when a frame exceeding the maximum length (set by RXFLH and RXFLL
registers) is received. When this error is detected, current frame reception is terminated.
Reception is stopped until the next START flag is detected.
3 ABORT 0 No abort pattern error in frame.
1 Abort pattern received. SIR and MIR: abort pattern. FIR: Illegal symbol.
2 CRC 0 No CRC error in frame.
1 CRC error in the frame at the top of the status FIFO (next character to be read).
1 STS_FIFO_E 0 Status FIFO is not empty.
1 Status FIFO is empty.
0 RX_FIFO_E 0 At least one data character in the RX FIFO.
1 No data in the receive FIFO.
3518
Universal Asynchronous Receiver/Transmitter (UART) SPRUH73H–October 2011–Revised April 2013
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