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Power, Reset, and Clock Management
8.1.13.7.2 RM_GFX_RSTCTRL Register (offset = 4h) [reset = 1h]
RM_GFX_RSTCTRL is shown in Figure 8-190 and described in Table 8-211.
This register controls the release of the GFX Domain resets.
Figure 8-190. RM_GFX_RSTCTRL Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved Reserved Reserved GFX_RST
R-0h R-0h R-0h R/W-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-211. RM_GFX_RSTCTRL Register Field Descriptions
Bit Field Type Reset Description
31-4 Reserved R 0h
3-2 Reserved R 0h
1 Reserved R 0h
0 GFX_RST R/W 1h
GFX domain local reset control
0x0 = CLEAR : Reset is cleared for the GFX Domain (SGX530)
0x1 = ASSERT : Reset is asserted for the GFX Domain (SGX 530)
741
SPRUH73H–October 2011–Revised April 2013 Power, Reset, and Clock Management (PRCM)
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