WDTimer1
PO_INT_PEND
PO_RSTCMD_N
PI_SYS_CLK
PRCM
PRCM
CLK_32KHZ
SEC_CLK32
PI_FREQ_RATIO
PI_SECURE_MODE
PI_SECURE_WD
PI_SECURE_WDA
PI_AUTO_START_DIS
PI_PTV_RESET_VALUE
PI_WLDR_RESET_VALUE
CLK_RC32K
L4 Wakeup
Interconnect
MPU Subsystem
WakeM3
000
0xFFFB0000
(10 s)
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WATCHDOG
20.4.2 Integration
The integration of the WD Timer is shown in Figure 20-96.
Figure 20-96. WDTimer Integration
20.4.2.1 Public WD Timer Connectivity Attributes
The general connectivity for the WD Timer module in this device is shown in Table 20-99.
Table 20-99. Public WD Timer Module Connectivity Attributes
Attributes Type
Power Domain Wakeup Domain
Clock Domain PD_WKUP_L4_WKUP_GCLK (OCP)
PD_WKUP_WDT1_GCLK (Func)
Reset Signals WKUP_DOM_RST_N
Idle/Wakeup Signals Smart Idle / Slave Wakeup
Interrupt Requests 1 Interrupt to MPU Subsystem (WDT1INT) and WakeM3
DMA Requests None
Physical Address L4 Wakeup slave port
20.4.2.2 Public WD Timer Clock and Reset Management
The Watchdog Timer functional clock (pi_sys_clk input) is sourced from either the on-chip ~32678 Hz
oscillator (CLK_RC32K) or the PER PLL generated 32.768 KHz clock (CLK_32KHZ) as selected using
CLKSEL_WDT1_CLK[CLKSEL] in the PRCM.
3671
SPRUH73H–October 2011–Revised April 2013 Timers
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