DMTimer 1ms
www.ti.com
20.2.5.11 TWPS Register (offset = 34h) [reset = 0h]
TWPS is shown in Figure 20-45 and described in Table 20-46.
This register contains the write posting bits for all writ-able functional registers
Figure 20-45. TWPS Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved W_PEND_TOWR W_PEND_TOCR
R-0h R-0h R-0h
7 6 5 4 3 2 1 0
W_PEND_TCVR W_PEND_TNIR W_PEND_TPIR W_PEND_TMAR W_PEND_TTGR W_PEND_TLDR W_PEND_TCRR W_PEND_TCLR
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-46. TWPS Register Field Descriptions
Bit Field Type Reset Description
31-10 Reserved R 0h
Reads return 0
9 W_PEND_TOWR R 0h
Write pending for register TOWR
0 = OWR_nPend : No Overflow Wrapping Register write pending.
1 = OWR_Pend : Overflow Wrapping Register write pending.
8 W_PEND_TOCR R 0h
Write pending for register TOCR
0 = OCR_nPend : No Overflow Counter Register write pending.
1 = OCR_Pend : Overflow Counter Register write pending.
7 W_PEND_TCVR R 0h
Write pending for register TCVR
0 = CVR_nPend : No Counter Register write pending.
1 = CVR_Pend : Counter Register write pending.
6 W_PEND_TNIR R 0h
Write pending for register TNIR
0 = NIR_nPend : No Negativ Increment Register write pending.
1 = NIR_Pend : Negativ Increment Register write pending.
5 W_PEND_TPIR R 0h
Write pending for register TPIR
0 = PIR_nPend : No Positive Increment Register write pending.
1 = PIR_Pend : Positive Increment Register write pending.
4 W_PEND_TMAR R 0h
Write pending for register TMAR
0 = MAR_nPend : No Match Register write pending
1 = MAR_Pend : Match Register write pending
3 W_PEND_TTGR R 0h
Write pending for register TTGR
0 = TGR_nPend : No Trigger Register write pending
1 = TGR_Pend : Trigger Register write pending
2 W_PEND_TLDR R 0h
Write pending for register TLDR
0 = LDR_nPend : No Load Register write pending
1 = LDR_Pend : Load Register write pending
1 W_PEND_TCRR R 0h
Write pending for register TCRR
0 = CRR_nPend : No Counter Register write pending
1 = CRR_Pend : Counter Register write pending
3610
Timers SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated