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CONTROL_MODULE Registers
9.3.4 control_status Register (offset = 40h) [reset = 0h]
control_status is shown in Figure 9-7 and described in Table 9-14.
Figure 9-7. control_status Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
sysboot1 testmd admux waiten bw
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
Reserved devtype
R-0h R-0h
7 6 5 4 3 2 1 0
sysboot0
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 9-14. control_status Register Field Descriptions
Bit Field Type Reset Description
31-24 Reserved R 0h
23-22 sysboot1 R/W 0h Used to select crystal clock frequency.
See SYSBOOT Configuration Pins.
Reset value is from SYSBOOT[15:14].
21-20 testmd R/W 0h Set to 00b.
See SYSBOOT Configuration Pins for more information.
Reset value is from SYSBOOT[13:12].
19-18 admux R/W 0h GPMC CS0 Default Address Muxing
00: No Addr/Data Muxing
01: Addr/Addr/Data Muxing
10: Addr/Data Muxing
11: Reserved
Reset value is from SYSBOOT[11:10].
17 waiten R/W 0h GPMC CS0 Default Wait Enable
0: Ignore WAIT input
1: Use WAIT input
See SYSBOOT Configuration Pins for more information. Reset value
is from SYSBOOT[9].
16 bw R/W 0h GPMC CS0 Default Bus Width
0: 8-bit data bus
1: 16-bit data bus
See SYSBOOT Configuration Pins for more information. Reset value
is from SYSBOOT[8].
15-11 Reserved R 0h
10-8 devtype R 0h 000: Reserved
001: Reserved
010: Reserved
011: General Purpose (GP) Device
111: Reserved
7-0 sysboot0 R/W 0h Selected boot mode.
See SYSBOOT Configuration Pins for more information.
Reset value is from SYSBOOT[7:0].
765
SPRUH73H–October 2011–Revised April 2013 Control Module
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