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WATCHDOG
20.4.4.1.4 WDT_WISR Register (offset = 18h) [reset = 0h]
WDT_WISR is shown in Figure 20-102 and described in Table 20-115.
The Watchdog Interrupt Status Register shows which interrupt events are pending inside the module.
Figure 20-102. WDT_WISR Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved DLY_IT_FLAG OVF_IT_FLAG
R-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-115. WDT_WISR Register Field Descriptions
Bit Field Type Reset Description
31-2 Reserved R 0h
1 DLY_IT_FLAG R/W 0h
Pending delay interrupt status.
0x0x0(W) = Status unchanged
0x0x0(R) = No delay interrupt pending
0x0x1(W) = Status bit cleared
0x0x1(R) = Delay interrupt pending
0 OVF_IT_FLAG R/W 0h
Pending overflow interrupt status.
0x0x0(W) = Status unchanged
0x0x0(R) = No overflow interrupt pending
0x0x1(W) = Status bit cleared
0x0x1(R) = Overflow interrupt pending
3685
SPRUH73H–October 2011–Revised April 2013 Timers
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