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16.5.7.6 FDBSC3 Register (offset = 2Ch) [reset = 0h]
FDBSC3 is shown in Figure 16-282 and described in Table 16-296.
Figure 16-282. FDBSC3 Register
31 30 29 28 27 26 25 24
FDBQ15_STARVE_CNT
R-0
23 22 21 20 19 18 17 16
FDBQ14_STARVE_CNT
R-0
15 14 13 12 11 10 9 8
FDBQ13_STARVE_CNT
R-0
7 6 5 4 3 2 1 0
FDBQ12_STARVE_CNT
R-0
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 16-296. FDBSC3 Register Field Descriptions
Bit Field Type Reset Description
31-24 FDBQ15_STARVE_CNT R-0 0 This field increments each time the Free Descriptor/Buffer Queue 15
is read while it is empty via the CPPI DMA.
This field is cleared when read via the cpu.
23-16 FDBQ14_STARVE_CNT R-0 0 This field increments each time the Free Descriptor/Buffer Queue 14
is read while it is empty via the CPPI DMA.
This field is cleared when read via the cpu.
15-8 FDBQ13_STARVE_CNT R-0 0 This field increments each time the Free Descriptor/Buffer Queue 13
is read while it is empty via the CPPI DMA.
This field is cleared when read via the cpu.
7-0 FDBQ12_STARVE_CNT R-0 0 This field increments each time the Free Descriptor/Buffer Queue 12
is read while it is empty via the CPPI DMA.
This field is cleared when read via the cpu.
Table
109 - QMGR_Free_Descriptor_Buffer_Starvation_Count Register 3
2114
Universal Serial Bus (USB) SPRUH73H–October 2011–Revised April 2013
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