www.ti.com
UART Registers
19.5.1.4 Interrupt Enable Register (IER) - IrDA Mode
The IrDA interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8
types of interrupt in these modes, received EOF, LSR interrupt, TX status, status FIFO interrupt, RX
overrun, last byte in RX FIFO, THR interrupt, and RHR interrupt. Each interrupt can be enabled/disabled
individually. The IrDA interrupt enable register (IER) is shown in Figure 19-37 and described in Table 19-
33.
NOTE: The TXSTATUSIT interrupt reflects two possible conditions. The MDR2[0] bit should be read
to determine the status in the event of this interrupt.
Figure 19-37. IrDA Interrupt Enable Register (IER)
15 8
Reserved
R-0
7 6 5 4 3 2 1 0
EOFIT LINESTSIT TXSTATUSIT STSFIFOTRIGIT RXOVERRUNIT LASTRXBYTEIT THRIT RHRIT
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-33. IrDA Interrupt Enable Register (IER) Field Descriptions
Bit Field Value Description
15-8 Reserved 0 Reserved.
7 EOFIT 0 Disables the received EOF interrupt.
1 Enables the received EOF interrupt.
6 LINESTSIT 0 Disables the receiver line status interrupt.
1 Enables the receiver line status interrupt.
5 TXSTATUSIT 0 Disables the TX status interrupt.
1 Enables the TX status interrupt.
4 STSFIFOTRIGIT 0 Disables status FIFO trigger level interrupt.
1 Enables status FIFO trigger level interrupt.
3 RXOVERRUNIT 0 Disables the RX overrun interrupt.
1 Enables the RX overrun interrupt.
2 LASTRXBYTEIT 0 Disables the last byte of frame in RX FIFO interrupt.
1 Enables the last byte of frame in RX FIFO interrupt.
1 THRIT 0 Disables the THR interrupt.
1 Enables the THR interrupt.
0 RHRIT 0 Disables the RHR interrupt.
1 Enables the RHR interrupt.
3509
SPRUH73H–October 2011–Revised April 2013 Universal Asynchronous Receiver/Transmitter (UART)
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
