USB Registers
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16.5.4.11 CDR_BIST2 Register (offset = 2Ch) [reset = 0h]
CDR_BIST2 is shown in Figure 16-144 and described in Table 16-155.
clock data recovery register and BIST register 2
Figure 16-144. CDR_BIST2 Register
31 30 29 28 27 26 25 24
CDR_EXE_EN CDR_EXE_MODE NUM_DECISIONS CDR_CHOSEN_PHA
SE
R/W-0h R/W-0h R/W-0h R-0h
23 22 21 20 19 18 17 16
CDR_CHOSEN_PHASE FORCE_CDR_PHASE DISABLE_CDR_FRE CDR_CONFIGURE
Q_TRACK
R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
CDR_CONFIGURE FORCE_CDR_PHAS Bist_start_addr
E_EN
R-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
Bist_start_addr Bist_end_addr
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 16-155. CDR_BIST2 Register Field Descriptions
Bit Field Type Reset Description
31 CDR_EXE_EN R/W 0h
CDR debug bits
30-28 CDR_EXE_MODE R/W 0h
CDR debug bits
27-25 NUM_DECISIONS R/W 0h
CDR debug bits
24-22 CDR_CHOSEN_PHASE R 0h
21-19 FORCE_CDR_PHASE R 0h
18 DISABLE_CDR_FREQ_T R 0h
RACK
17-13 CDR_CONFIGURE R 0h
12 FORCE_CDR_PHASE_E R 0h Use bits
N 21-19 as the phase to be forced on the CDR.
11-6 Bist_start_addr R/W 0h
See DFT spec for details
5-0 Bist_end_addr R/W 0h
See DFT spec for details
1916
Universal Serial Bus (USB) SPRUH73H–October 2011–Revised April 2013
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