Power, Reset, and Clock Management
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8.1.13.6.2 PM_RTC_PWRSTST Register (offset = 4h) [reset = 4h]
PM_RTC_PWRSTST is shown in Figure 8-188 and described in Table 8-208.
This register provides a status on the current RTC power domain state0. [warm reset insensitive]
Figure 8-188. PM_RTC_PWRSTST Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved InTransition Reserved
R-0h R-0h R-0h
15 14 13 12 11 10 9 8
Reserved Reserved
R-0h R-0h
7 6 5 4 3 2 1 0
Reserved Reserved LogicStateSt Reserved
R-0h R-0h R-1h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-208. PM_RTC_PWRSTST Register Field Descriptions
Bit Field Type Reset Description
31-21 Reserved R 0h
20 InTransition R 0h
Domain transition status
0x0 = No : No on-going transition on power domain
0x1 = Ongoing : Power domain transition is in progress.
19-10 Reserved R 0h
9-4 Reserved R 0h
3 Reserved R 0h
2 LogicStateSt R 1h
Logic state status
0x0 = OFF : Logic in domain is OFF
0x1 = ON : Logic in domain is ON
1-0 Reserved R 0h
8.1.13.7 PRM_GFX Registers
Table 8-209 lists the memory-mapped registers for the PRM_GFX. All register offset addresses not listed
in Table 8-209 should be considered as reserved locations and the register contents should not be
modified.
Table 8-209. PRM_GFX REGISTERS
Offset Acronym Register Name Section
0h PM_GFX_PWRSTCTRL This register controls the GFX power state to reach upon Section 8.1.13.7.1
a domain sleep transition.
4h RM_GFX_RSTCTRL This register controls the release of the GFX Domain Section 8.1.13.7.2
resets.
10h PM_GFX_PWRSTST This register provides a status on the current GFX power Section 8.1.13.7.3
domain state.
[warm reset insensitive]
14h RM_GFX_RSTST This register logs the different reset sources of the GFX Section 8.1.13.7.4
domain.
Each bit is set upon release of the domain reset signal.
Must be cleared by software.
[warm reset insensitive]
738
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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