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UART Registers
19.5.1.1 Receiver Holding Register (RHR)
The receiver section consists of the receiver holding register and the receiver shift register. The RHR is
actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is
converted to parallel data and moved to the RHR. If the FIFO is disabled, location zero of the FIFO is
used to store the single data character.
NOTE: If an overflow occurs, the data in the RHR is not overwritten.
The receiver holding register (RHR) register is shown in Figure 19-34 and described in Table 19-30.
Figure 19-34. Receiver Holding Register (RHR)
15 8 7 0
Reserved RHR
R-0 R-unknown
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-30. Receiver Holding Register (RHR) Field Descriptions
Bit Field Value Description
15-8 Reserved 0 Reserved.
7-0 RHR 0-FFh Receive holding register.
19.5.1.2 Transmit Holding Register (THR)
The transmitter section consists of the transmit holding register and the transmit shift register. The
transmit holding register is a 64-byte FIFO. The MPU writes data to the THR. The data is placed in the
transmit shift register where it is shifted out serially on the TX output. If the FIFO is disabled, location zero
of the FIFO is used to store the data.
The transmit holding register (THR) is shown in Figure 19-35 and described in Table 19-31.
Figure 19-35. Transmit Holding Register (THR)
15 8 7 0
Reserved THR
R-0 W-unknown
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 19-31. Transmit Holding Register (THR) Field Descriptions
Bit Field Value Description
15-8 Reserved 0 Reserved.
7-0 THR 0-FFh Transmit holding register.
3507
SPRUH73H–October 2011–Revised April 2013 Universal Asynchronous Receiver/Transmitter (UART)
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