WATCHDOG
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20.4.4.1.7 WDT_WCRR Register (offset = 28h) [reset = 0h]
WDT_WCRR is shown in Figure 20-105 and described in Table 20-118.
The Watchdog Counter Register holds the value of the internal counter.
Figure 20-105. WDT_WCRR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMER_COUNTER
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-118. WDT_WCRR Register Field Descriptions
Bit Field Type Reset Description
31-0 TIMER_COUNTER R/W 0h
Value of the timer counter register
3688
Timers SPRUH73H–October 2011–Revised April 2013
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