Ethernet Subsystem Registers
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14.5.9.4 INT_CONTROL Register (offset = Ch) [reset = 0h]
INT_CONTROL is shown in Figure 14-200 and described in Table 14-218.
SUBSYSTEM INTERRUPT CONTROL
Figure 14-200. INT_CONTROL Register
31 30 29 28 27 26 25 24
INT_TEST Reserved
R/W-0h R-0h
23 22 21 20 19 18 17 16
Reserved INT_PACE_EN
R-0h R/W-0h
15 14 13 12 11 10 9 8
Reserved INT_PRESCALE
R-0h R-0h
7 6 5 4 3 2 1 0
INT_PRESCALE
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-218. INT_CONTROL Register Field Descriptions
Bit Field Type Reset Description
31 INT_TEST R/W 0h
Interrupt Test - Test bit to the interrupt pacing blocks
30-22 Reserved R 0h
21-16 INT_PACE_EN R/W 0h
Interrupt Pacing Enable Bus int_pace_en[0] - Enables C0_Rx_Pulse
Pacing (0 is pacing bypass) int_pace_en[1] - Enables C0_Tx_Pulse
Pacing (0 is pacing bypass) int_pace_en[2] - Enables C1_Rx_Pulse
Pacing (0 is pacing bypass) int_pace_en[3] - Enables C1_Tx_Pulse
Pacing (0 is pacing bypass) int_pace_en[4] - Enables C2_Rx_Pulse
Pacing (0 is pacing bypass) int_pace_en[5] - Enables C2_Tx_Pulse
Pacing (0 is pacing bypass)
15-12 Reserved R 0h
11-0 INT_PRESCALE R 0h
Interrupt Counter Prescaler - The number of MAIN_CLK periods in
4us.
1442
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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