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Power, Reset, and Clock Management
8.1.13.5.2 PRM_RSTTIME Register (offset = 4h) [reset = 1006h]
PRM_RSTTIME is shown in Figure 8-180 and described in Table 8-199.
Reset duration control. [warm reset insensitive]
Figure 8-180. PRM_RSTTIME Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved RSTTIME2
R-0h R/W-10h
7 6 5 4 3 2 1 0
RSTTIME1
R/W-6h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-199. PRM_RSTTIME Register Field Descriptions
Bit Field Type Reset Description
31-13 Reserved R 0h
12-8 RSTTIME2 R/W 10h
(Power domain) reset duration 2 (number of CLK_M_OSC clock
cycles)
7-0 RSTTIME1 R/W 6h
(Global) reset duration 1 (number of CLK_M_OSC clock cycles)
727
SPRUH73H–October 2011–Revised April 2013 Power, Reset, and Clock Management (PRCM)
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