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Touchscreen Controller Registers
12.5.1.3 IRQSTATUS_RAW Register (offset = 24h) [reset = 0h]
IRQSTATUS_RAW is shown in Figure 12-7 and described in Table 12-7.
IRQ status (unmasked)
Figure 12-7. IRQSTATUS_RAW Register
31 30 29 28 27 26 25 24
Reserved
R/W-0h
23 22 21 20 19 18 17 16
Reserved
R/W-0h
15 14 13 12 11 10 9 8
Reserved PEN_IRQ_synchroniz Pen_Up_Event Out_of_Range
ed
R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
FIFO1_Underflow FIFO1_Overrun FIFO1_Threshold FIFO0_Underflow FIFO0_Overrun FIFO0_Threshold End_of_Sequence HW_Pen_Event_asyn
chronous
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-7. IRQSTATUS_RAW Register Field Descriptions
Bit Field Type Reset Description
31-11 Reserved R/W 0h
10 PEN_IRQ_synchronized R/W 0h Write 0 = No action.
Write 1 = Set event (debug).
Read 0 = No event pending.
Read 1 = Event pending.
9 Pen_Up_Event R/W 0h Write 0 = No action.
Write 1 = Set event (debug).
Read 0 = No event pending.
Read 1 = Event pending.
8 Out_of_Range R/W 0h Write 0 = No action.
Write 1 = Set event (debug).
Read 0 = No event pending.
Read 1 = Event pending.
7 FIFO1_Underflow R/W 0h Write 0 = No action.
Write 1 = Set event (debug).
Read 0 = No event pending.
Read 1 = Event pending.
6 FIFO1_Overrun R/W 0h Write 0 = No action.
Write 1 = Set event (debug).
Read 0 = No event pending.
Read 1 = Event pending.
5 FIFO1_Threshold R/W 0h Write 0 = No action.
Write 1 = Set event (debug).
Read 0 = No event pending.
Read 1 = Event pending.
4 FIFO0_Underflow R/W 0h Write 0 = No action.
Write 1 = Set event (debug).
Read 0 = No event pending.
Read 1 = Event pending.
3 FIFO0_Overrun R/W 0h Write 0 = No action.
Write 1 = Set event (debug).
Read 0 = No event pending.
Read 1 = Event pending.
1037
SPRUH73H–October 2011–Revised April 2013 Touchscreen Controller
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