DMTimer 1ms
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20.2.5.6 TWER Register (offset = 20h) [reset = 0h]
TWER is shown in Figure 20-40 and described in Table 20-41.
This register controls (enable/disable) the wakeup feature on specific interrupt events
Figure 20-40. TWER Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved TCAR_WUP_ENA OVF_WUP_ENA MAT_WUP_ENA
R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-41. TWER Register Field Descriptions
Bit Field Type Reset Description
31-3 Reserved R 0h
Reads return 0
2 TCAR_WUP_ENA R/W 0h
Enable capture wake-up
0 = DsbWupCap : Disable capture wake-up
1 = EnbWupCapt : Enable capture wake-up
1 OVF_WUP_ENA R/W 0h
Enable overflow wake-up
0 = DsbWupOvf : Disable overflow wake-up
1 = EnbWupOvf : Enable overflow wake-up
0 MAT_WUP_ENA R/W 0h
Enable match wake-up
0 = DsbWupMat : Disable match wake-up
1 = EnbWupMat : Enable match wake-up
3604
Timers SPRUH73H–October 2011–Revised April 2013
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