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GPIO Registers
25.4.1.9 GPIO_IRQSTATUS_SET_1 Register (offset = 38h) [reset = 0h]
GPIO_IRQSTATUS_SET_1 is shown in Figure 25-15 and described in Table 25-14.
All 1-bit fields in the GPIO_IRQSTATUS_SET_1 register enable a specific interrupt event to trigger an
interrupt request. Writing a 1 to a bit enables the interrupt field. Writing a 0 has no effect, that is, the
register value is not modified.
Figure 25-15. GPIO_IRQSTATUS_SET_1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTLINE[n]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 25-14. GPIO_IRQSTATUS_SET_1 Register Field Descriptions
Bit Field Type Reset Description
31-0 INTLINE[n] R/W 0h
Interrupt n enable
0x0 = No effect.
0x1 = Enable IRQ generation.
4077
SPRUH73H–October 2011–Revised April 2013 General-Purpose Input/Output
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