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EMIF
7.3.5.5 SDRAM_REF_CTRL Register (offset = 10h) [reset = 0h]
SDRAM_REF_CTRL is shown in Figure 7-95 and described in Table 7-115.
Figure 7-95. SDRAM_REF_CTRL Register
31 30 29 28 27 26 25 24
reg_initref_dis Reserved reg_srt reg_asr Reserved reg_pasr
R/W-0h R-0h R/W-0h R/W-0h R-0h R/W-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
reg_refresh_rate
R/W-0h
7 6 5 4 3 2 1 0
reg_refresh_rate
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-115. SDRAM_REF_CTRL Register Field Descriptions
Bit Field Type Reset Description
31 reg_initref_dis R/W 0h Initialization and Refresh disable.
When set to 1, EMIF will disable SDRAM initialization and refreshes,
but will carry out SDRAM write/read transactions.
30 Reserved R 0h
29 reg_srt R/W 0h DDR3 Self Refresh temperature range.
Set to 0 for normal operating temperature range and set to 1 for
extended operating temperature range when the reg_asr field is set
to 0.
This bit must be set to 0 if the reg_asr field is set to 1.
A write to this field will cause the EMIF to start the SDRAM
initialization sequence.
28 reg_asr R/W 0h DDR3 Auto Self Refresh enable.
Set to 1 for auto Self Refresh enable.
Set to 0 for manual Self Refresh reference indicated by the reg_srt
field.
A write to this field will cause the EMIF to start the SDRAM
initialization sequence.
27 Reserved R 0h
26-24 reg_pasr R/W 0h Partial Array Self Refresh.
These bits get loaded into the Extended Mode Register of an
LPDDR1 or DDR3 during initialization.
For LPDDR1, set to 0 for full array, set to 1 for 1/2 array, set to 2 for
1/4 array, set to 5 for 1/8 array, and set to 6 for 1/16 array to be
refreshed.
For DDR3, set to 0 for full array, set to 1 or 5 for 1/2 array, set to 2
or 6 for 1/4 array, set to 3 or 7 for 1/8 array, and set to 4 for 3/4
array to be refreshed.
All other values are reserved.
A write to this field will cause the EMIF to start the SDRAM
initialization sequence.
23-16 Reserved R 0h
15-0 reg_refresh_rate R/W 0h Refresh Rate.
Value in this field is used to define the rate at which connected
SDRAM devices will be refreshed.
SDRAM refresh rate = EMIF rate / reg_refresh_rate where EMIF rate
is equal to DDR clock rate.
If reg_refresh_rate < (8*reg_t_rfc)+reg_t_rp+reg_t_rcd+20 then it will
be loaded with (8*reg_t_rfc)+reg_t_rp+reg_t_rcd+20.
This is done to avoid lock-up situations when illegal values are
programmed.
429
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
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