GPMC
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• Pre-fetch and write posting engine associated with system DMA to get full performance from NAND
device with minimum impact on NOR/SRAM concurrent access.
• On the fly ECC Hamming Code calculation to improve NAND usage reliability with minimum impact on
SW
7.1.1.2 Block Diagram
The GPMC can access various external devices through the L3 Slow Interconnect. The flexible
programming model allows a wide range of attached device types and access schemes. Based on the
programmed configuration bit fields stored in the GPMC registers, the GPMC is able to generate all
control signals timing depending on the attached device and access type. Given the chip-select decoding
and its associated configuration registers, the GPMC selects the appropriate device type control signals
timing.
Figure 7-1 shows the GPMC functional block diagram. The GPMC consists of six blocks:
• Interconnect port interface
• Address decoder, GPMC configuration, and chip-select configuration register file
• Access engine
• Prefetch and write-posting engine
• Error correction code engine (ECC)
• External device/memory port interface
252
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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