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CONTROL_MODULE Registers
9.3.39 smrt_ctrl Register (offset = 6A0h) [reset = 0h]
smrt_ctrl is shown in Figure 9-42 and described in Table 9-49.
Figure 9-42. smrt_ctrl Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved sr1_sleep sr0_sleep
R-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 9-49. smrt_ctrl Register Field Descriptions
Bit Field Type Reset Description
31-2 Reserved R 0h
1 sr1_sleep R/W 0h 0: Disable sensor (SRSLEEP on sensor driven to 1)
1: Enable sensor (SRSLEEP on sensor driven to 0).
0 sr0_sleep R/W 0h 0: Disable sensor (SRSLEEP on sensor driven to 1)
1: Enable sensor (SRSLEEP on sensor driven to 0).
803
SPRUH73H–October 2011–Revised April 2013 Control Module
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