DCAN Registers
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23.4.32 INTMUX78 Register (offset = E4h) [reset = 0h]
INTMUX78 is shown in Figure 23-50 and described in Table 23-45.
The IntMux flag determine for each message object, which of the two interrupt lines (DCAN0INT or
DCAN1INT) will be asserted when the IntPnd of this message object is set. Both interrupt lines can be
globally enabled or disabled by setting or clearing IE0 and IE1 bits in CAN control register. The IntPnd bit
of a specific message object can be set or reset by the CPU via the IF1/IF2 interface register sets, or by
message handler after reception or successful transmission of a frame. This will also affect the Int0ID resp
Int1ID flags in the interrupt register.
Figure 23-50. INTMUX78 Register
31 30 29 28 27 26 25 24
IntMux[128:113]
R-0h
23 22 21 20 19 18 17 16
IntMux[128:113]
R-0h
15 14 13 12 11 10 9 8
IntMux[112:97]
R-0h
7 6 5 4 3 2 1 0
IntMux[112:97]
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 23-45. INTMUX78 Register Field Descriptions
Bit Field Type Reset Description
31-16 IntMux[128:113] R 0h
Multiplexes IntPnd value to either DCAN0INT or DCAN1INT interrupt
lines (for all message objects)
0x0 = DCAN0INT line is active if corresponding IntPnd flag is one.
0x1 = DCAN1INT line is active if corresponding IntPnd flag is one.
15-0 IntMux[112:97] R 0h
Multiplexes IntPnd value to either DCAN0INT or DCAN1INT interrupt
lines (for all message objects)
0x0 = DCAN0INT line is active if corresponding IntPnd flag is one.
0x1 = DCAN1INT line is active if corresponding IntPnd flag is one.
3958
Controller Area Network (CAN) SPRUH73H–October 2011–Revised April 2013
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