If the configuration set in the SDVS field is
not compliant with the supported voltage set
in the SD_CAPA register, SDBP returns to 0x0.
For initialization sequence, you should have
80 clock cycles in 1ms.
It means clock frequency should be 80 kHz≤
Start
Write SD_HCTL register
(SDVS, SDBP, DTW) to configure the card voltage
value and power mode and data bus width
SDBP = 0x1 ?
End
YES
NO
Read back the
SD_HCTL[8] SDBP bit
Set the SD_SYSCTL[0] ICE
bit to 0x1 to enable the internal clock
Configure the
SD_SYSCTL[15:6] CLKD
bit field
Read the SD_SYSCTL[1] ICS bit
ICS = 0x1 ?
YES
Clock is stable
Write the SD_SYSCONFIG
CLOCKACTIVITY, SIDLEMODE, and
AUTOIDLE fields to configure the
behavior of the module in idle mode
NO
Write SD_CON register
to configure specific
data and command transfer
(OD, DW8, CEATA)
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