Ethernet Subsystem Registers
www.ti.com
14.5.6.52 P2_RX_DSCP_PRI_MAP7 Register (offset = 24Ch) [reset = 0h]
P2_RX_DSCP_PRI_MAP7 is shown in Figure 14-172 and described in Table 14-187.
CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 7
Figure 14-172. P2_RX_DSCP_PRI_MAP7 Register
31 30 29 28 27 26 25 24
Reserved PRI63 Reserved PRI62
R/W-0h R/W-0h
23 22 21 20 19 18 17 16
Reserved PRI61 Reserved PRI60
R/W-0h R/W-0h
15 14 13 12 11 10 9 8
Reserved PRI59 Reserved PRI58
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved PRI57 Reserved PRI56
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-187. P2_RX_DSCP_PRI_MAP7 Register Field Descriptions
Bit Field Type Reset Description
30-28 PRI63 R/W 0h Priority
63 - A packet TOS of 0d63 is mapped to this received packet
priority.
26-24 PRI62 R/W 0h Priority
62 - A packet TOS of 0d62 is mapped to this received packet
priority.
22-20 PRI61 R/W 0h Priority
61 - A packet TOS of 0d61 is mapped to this received packet
priority.
18-16 PRI60 R/W 0h Priority
60 - A packet TOS of 0d60 is mapped to this received packet
priority.
14-12 PRI59 R/W 0h Priority
59 - A packet TOS of 0d59 is mapped to this received packet
priority.
10-8 PRI58 R/W 0h Priority
58 - A packet TOS of 0d58 is mapped to this received packet
priority.
6-4 PRI57 R/W 0h Priority
57 - A packet TOS of 0d57 is mapped to this received packet
priority.
2-0 PRI56 R/W 0h Priority
56 - A packet TOS of 0d56 is mapped to this received packet
priority.
14.5.7 CPSW_SL Registers
Table 14-188 lists the memory-mapped registers for the CPSW_SL. All register offset addresses not listed
in Table 14-188 should be considered as reserved locations and the register contents should not be
modified.
1410
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
