www.ti.com
Ethernet Subsystem Registers
Table 14-188. CPSW_SL REGISTERS
Offset Acronym Register Name Section
0h IDVER CPGMAC_SL ID/VERSION REGISTER Section 14.5.7.1
4h MACCONTROL CPGMAC_SL MAC CONTROL REGISTER Section 14.5.7.2
8h MACSTATUS CPGMAC_SL MAC STATUS REGISTER Section 14.5.7.3
Ch SOFT_RESET CPGMAC_SL SOFT RESET REGISTER Section 14.5.7.4
10h RX_MAXLEN CPGMAC_SL RX MAXIMUM LENGTH REGISTER Section 14.5.7.5
14h BOFFTEST CPGMAC_SL BACKOFF TEST REGISTER Section 14.5.7.6
18h RX_PAUSE CPGMAC_SL RECEIVE PAUSE TIMER REGISTER Section 14.5.7.7
1Ch TX_PAUSE CPGMAC_SL TRANSMIT PAUSE TIMER REGISTER Section 14.5.7.8
20h EMCONTROL CPGMAC_SL EMULATION CONTROL REGISTER Section 14.5.7.9
24h RX_PRI_MAP CPGMAC_SL RX PKT PRIORITY TO HEADER Section 14.5.7.10
PRIORITY MAPPING REGISTER
28h TX_GAP TRANSMIT INTER-PACKET GAP REGISTER Section 14.5.7.11
1411
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
