I2C Registers
www.ti.com
21.4.1.15 I2C_SYSS Register (offset = 90h) [reset = 0h]
I2C_SYSS is shown in Figure 21-30 and described in Table 21-23.
Figure 21-30. I2C_SYSS Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved RDONE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 21-23. I2C_SYSS Register Field Descriptions
Bit Field Type Reset Description
31-1 Reserved R 0h
0 RDONE R/W 0h Reset done bit.
This read-only bit indicates the state of the reset in case of hardware
reset, global software reset (I2C_SYSC.SRST) or partial software
reset (I2C_CON.I2C_EN).
The module must receive all its clocks before it can grant a reset-
completed status.
Value after reset is low.
0x0 = Internal module reset in ongoing
0x1 = Reset completed
3744
I2C SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
