Texas Instruments AM335 Series Technical Reference Manual

Ethernet Subsystem Registers www.ti.com
14.5.2.21 TX_INTSTAT_MASKED Register (offset = 84h) [reset = 0h]
TX_INTSTAT_MASKED is shown in Figure 14-49 and described in Table 14-60.
CPDMA_INT TX INTERRUPT STATUS REGISTER (MASKED VALUE)
Figure 14-49. TX_INTSTAT_MASKED Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
TX7_PEND TX6_PEND TX5_PEND TX4_PEND TX3_PEND TX2_PEND TX1_PEND TX0_PEND
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-60. TX_INTSTAT_MASKED Register Field Descriptions
Bit Field Type Reset Description
31-8 Reserved R 0h
7 TX7_PEND R 0h
TX7_PEND masked interrupt read.
6 TX6_PEND R 0h
TX6_PEND masked interrupt read.
5 TX5_PEND R 0h
TX5_PEND masked interrupt read.
4 TX4_PEND R 0h
TX4_PEND masked interrupt read.
3 TX3_PEND R 0h
TX3_PEND masked interrupt read.
2 TX2_PEND R 0h
TX2_PEND masked interrupt read.
1 TX1_PEND R 0h
TX1_PEND masked interrupt read.
0 TX0_PEND R 0h
TX0_PEND masked interrupt read.
1280
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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Texas Instruments AM335 Series Specifications

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Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English