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7.3.5.10 SDRAM_TIM_2_SHDW Register (offset = 24h) [reset = 0h]
SDRAM_TIM_2_SHDW is shown in Figure 7-100 and described in Table 7-120.
Figure 7-100. SDRAM_TIM_2_SHDW Register
31 30 29 28 27 26 25 24
Reserved reg_t_xp_shdw reg_t_odt_shdw reg_t_xsnr_shdw
R-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
reg_t_xsnr_shdw
R/W-0h
15 14 13 12 11 10 9 8
reg_t_xsrd_shdw
R/W-0h
7 6 5 4 3 2 1 0
reg_t_xsrd_shdw reg_t_rtp_shdw reg_t_cke_shdw
R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-120. SDRAM_TIM_2_SHDW Register Field Descriptions
Bit Field Type Reset Description
31 Reserved R 0h
30-28 reg_t_xp_shdw R/W 0h Shadow field for reg_t_xp.
This field is loaded into reg_t_xp field in SDRAM Timing 2 register
when SIdleAck is asserted.
27-25 reg_t_odt_shdw R/W 0h Shadow field for reg_t_odt.
This field is loaded into reg_t_odt field in SDRAM Timing 2 register
when SIdleAck is asserted.
24-16 reg_t_xsnr_shdw R/W 0h Shadow field for reg_t_xsnr.
This field is loaded into reg_t_xsnr field in SDRAM Timing 2 register
when SIdleAck is asserted.
15-6 reg_t_xsrd_shdw R/W 0h Shadow field for reg_t_xsrd.
This field is loaded into reg_t_xsrd field in SDRAM Timing 2 register
when SIdleAck is asserted.
5-3 reg_t_rtp_shdw R/W 0h Shadow field for reg_t_rtp.
This field is loaded into reg_t_rtp field in SDRAM Timing 2 register
when SIdleAck is asserted.
2-0 reg_t_cke_shdw R/W 0h Shadow field for reg_t_cke.
This field is loaded into reg_t_cke field in SDRAM Timing 2 register
when SIdleAck is asserted.
434
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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