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WATCHDOG
20.4.4.1.10 WDT_WWPS Register (offset = 34h) [reset = 0h]
WDT_WWPS is shown in Figure 20-108 and described in Table 20-121.
The Watchdog Write Posting Bits Register contains the write posting bits for all writeable functional
registers.
Figure 20-108. WDT_WWPS Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved W_PEND_WDLY W_PEND_WSPR W_PEND_WTGR W_PEND_WLDR W_PEND_WCRR W_PEND_WCLR
R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-121. WDT_WWPS Register Field Descriptions
Bit Field Type Reset Description
31-6 Reserved R 0h
5 W_PEND_WDLY R 0h
Write pending for register WDLY
0x0 = No register write pending
0x1 = Register write pending
4 W_PEND_WSPR R 0h
Write pending for register WSPR
0x0 = No register write pending
0x1 = Register write pending
3 W_PEND_WTGR R 0h
Write pending for register WTGR
0x0 = No register write pending
0x1 = Register write pending
2 W_PEND_WLDR R 0h
Write pending for register WLDR
0x0 = No register write pending
0x1 = Register write pending
1 W_PEND_WCRR R 0h
Write pending for register WCRR
0x0 = No register write pending
0x1 = Register write pending
0 W_PEND_WCLR R 0h
Write pending for register WCLR
0x0 = No register write pending
0x1 = Register write pending
3691
SPRUH73H–October 2011–Revised April 2013 Timers
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