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Functional Description
27.1 Functional Description
27.1.1 Debug Suspend Support for Peripherals
When a processor is halted, peripherals associated with the processor must appropriately respond to this
event to avoid incorrect actions.
An example of this is the action of the Watchdog Timer (WDT) during a debug halt. Typically watchdog
timers fire a reset to restart a system after a timeout. The reset could be misfired during debug if a
processor is halted for a fairly long time and prevents a WDT monitor from refreshing the timer.
To prevent this incorrect action, the watchdog timer supports a debug suspend event. This event allows
the WDT to stop counting during a CPU halt.
Other peripherals also support a debug suspend event. The list of supported peripherals is shown in
Table 27-1.
Recommended Suspend Control Register Value:
Normal mode: 0x0
Suspend peripheral during debug halt: 0x9
27.1.1.1 Debug Subsystem Registers
Table 27-1. Debug Subsystem Registers
Offset Peripheral Register Name
200h Watchdog Timer Watchdog_Timer_Suspend_Control
204h DMTimer-0 DMTimer_0_Suspend_Control
208h DMTimer-1 DMTimer_1_Suspend_Control
20Ch DMTimer-2 DMTimer_2_Suspend_Control
210h DMTimer-3 DMTimer_3_Suspend_Control
214h DMTimer-4 DMTimer_4_Suspend_Control
218h DMTimer-5 DMTimer_5_Suspend_Control
21Ch DMTimer-6 DMTimer_6_Suspend_Control
220h EMAC EMAC_Suspend_Control
224h USB2.0 USB2_Suspend_Control
228h I2C-0 I2C_0_Suspend_Control
22Ch I2C-1 I2C_1__Suspend_Control
230h I2C-2 I2C_2_Suspend_Control
234h eHRPWM-0 eHRPWM_0_Suspend_Control
238h eHRPWM-1 eHRPWM_1_Suspend_Control
23Ch eHRPWM-2 eHRPWM_2_Suspend_Control
240h CAN-0 CAN_0_Suspend_Control
244h CAN-1 CAN_1_Suspend_Control
248h PRU-ICSS PRU_ICSS_Suspend_Control
260h DMTimer-7 DMTimer_7_Suspend_Control
4157
SPRUH73H–October 2011–Revised April 2013 Debug Subsystem
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