www.ti.com
GPMC
7.1.4.1.5 GPMC Configuration for Asynchronous Single Write Access
The clock runs at 104 MHz: (f = 104 MHz; T = 9, 615 ns).
Table 7-50 shows how to calculate timings for the GPMC using the memory parameters.
Table 7-51 shows the timing parameters (on the memory side) that determine the parameters on the
GPMC side.
Figure 7-50 shows the synchronous burst write access.
Table 7-50. AC Characteristics for Asynchronous Single Write (Memory Side)
AC Characteristics on the
Description Duration (ns)
Memory Side
tWC Write cycle time 60
tAVDP ADVn low time 6
tWP Write pulse width 25
tWPH Write pulse width high 20
tCS CSn setup time to WEn 3
tCAS CSn setup time to ADVn 0
tAVSC ADVn setup time 3
For asynchronous single write access, write cycle time is WrCycleTime = WeOffTime + AccessCompletion
= WeOffTime + 1. For the AccesCompletion, the GPMC requires 1 cycle of data hold time (CSn de-
assertion).
361
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
