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Power, Reset, and Clock Management
8.1.12.2.1 CM_WKUP_CLKSTCTRL Register (offset = 0h) [reset = 6h]
CM_WKUP_CLKSTCTRL is shown in Figure 8-84 and described in Table 8-92.
This register enables the domain power state transition. It controls the SW supervised clock domain state
transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the
domain.
Figure 8-84. CM_WKUP_CLKSTCTRL Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved CLKACTIVITY_ADC_ CLKACTIVITY_TIME CLKACTIVITY_UART CLKACTIVITY_I2C0_ CLKACTIVITY_TIME Reserved CLKACTIVITY_GPIO0
FCLK R1_GCLK 0_GFCLK GFCLK R0_GCLK _GDBCLK
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
Reserved CLKACTIVITY_WDT1 CLKACTIVITY_SR_S CLKACTIVITY_L4_W CLKTRCTRL
_GCLK YSCLK KUP_GCLK
R-0h R-0h R-0h R-1h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-92. CM_WKUP_CLKSTCTRL Register Field Descriptions
Bit Field Type Reset Description
31-15 Reserved R 0h
14 CLKACTIVITY_ADC_FCL R 0h
This field indicates the state of the ADC clock in the domain.
K
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
13 CLKACTIVITY_TIMER1_ R 0h
This field indicates the state of the TIMER1 clock in the domain.
GCLK
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
12 CLKACTIVITY_UART0_G R 0h
This field indicates the state of the UART0 clock in the domain.
FCLK
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
11 CLKACTIVITY_I2C0_GFC R 0h
This field indicates the state of the I2C0 clock in the domain.
LK
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
10 CLKACTIVITY_TIMER0_ R 0h
This field indicates the state of the WKUPTIMER_GCLK clock in the
GCLK
domain.
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
9 Reserved R 0h
8 CLKACTIVITY_GPIO0_G R 0h
This field indicates the state of the WKUPGPIO_DBGICLK clock in
DBCLK
the domain.
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
7-5 Reserved R 0h
4 CLKACTIVITY_WDT1_G R 0h
This field indicates the state of the WDT1_GCLK clock in the
CLK
domain.
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
615
SPRUH73H–October 2011–Revised April 2013 Power, Reset, and Clock Management (PRCM)
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