Power, Reset, and Clock Management
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Table 8-91. CM_WKUP REGISTERS (continued)
Offset Acronym Register Name Section
C8h CM_WKUP_SMARTREFLEX1_CL This register manages the SmartReflex1 clocks. Section 8.1.12.2.51
KCTRL
CCh CM_L4_WKUP_AON_CLKSTCTR This register enables the domain power state transition. Section 8.1.12.2.52
L It controls the SW supervised clock domain state
transition between ON-ACTIVE and ON-INACTIVE
states.
It also hold one status bit per clock input of the domain.
D4h CM_WKUP_WDT1_CLKCTRL This register manages the WDT1 clocks. Section 8.1.12.2.53
D8h CM_DIV_M6_DPLL_CORE This register provides controls over the CLKOUT3 o/p of Section 8.1.12.2.54
the HSDIVIDER.
[warm reset insensitive]
614
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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