EMIF
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7.3.5.8 SDRAM_TIM_1_SHDW Register (offset = 1Ch) [reset = 0h]
SDRAM_TIM_1_SHDW is shown in Figure 7-98 and described in Table 7-118.
Figure 7-98. SDRAM_TIM_1_SHDW Register
31 30 29 28 27 26 25 24
Reserved reg_t_rp_shdw reg_t_rcd_shdw
R-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
reg_t_rcd_shdw reg_t_wr_shdw reg_t_ras_shdw
R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
reg_t_ras_shdw reg_t_rc_shdw
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
reg_t_rc_shdw reg_t_rrd_shdw reg_t_wtr_shdw
R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-118. SDRAM_TIM_1_SHDW Register Field Descriptions
Bit Field Type Reset Description
31-29 Reserved R 0h
28-25 reg_t_rp_shdw R/W 0h Shadow field for reg_t_rp.
This field is loaded into reg_t_rp field in SDRAM Timing 1 register
when SIdleAck is asserted.
24-21 reg_t_rcd_shdw R/W 0h Shadow field for reg_t_rcd.
This field is loaded into reg_t_rcd field in SDRAM Timing 1 register
when SIdleAck is asserted.
20-17 reg_t_wr_shdw R/W 0h Shadow field for reg_t_wr.
This field is loaded into reg_t_wr field in SDRAM Timing 1 register
when SIdleAck is asserted.
initialization sequence will be started when the value of this field is
changed from the previous value and the EMIF is in DDR2 mode.
16-12 reg_t_ras_shdw R/W 0h Shadow field for reg_t_ras.
This field is loaded into reg_t_ras field in SDRAM Timing 1 register
when SIdleAck is asserted.
11-6 reg_t_rc_shdw R/W 0h Shadow field for reg_t_rc.
This field is loaded into reg_t_rc field in SDRAM Timing 1 register
when SIdleAck is asserted.
5-3 reg_t_rrd_shdw R/W 0h Shadow field for reg_t_rrd.
This field is loaded into reg_t_rrd field in SDRAM Timing 1 register
when SIdleAck is asserted.
2-0 reg_t_wtr_shdw R/W 0h Shadow field for reg_t_wtr.
This field is loaded into reg_t_wtr field in SDRAM Timing 1 register
when SIdleAck is asserted.
432
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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