Texas Instruments AM335 Series Technical Reference Manual

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14.5.5.32 RX7_CP Register (offset = A7Ch) [reset = 0h]
RX7_CP is shown in Figure 14-120 and described in Table 14-134.
CPDMA_STATERAM RX CHANNEL 7 COMPLETION POINTER REGISTER *
Figure 14-120. RX7_CP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_CP
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-134. RX7_CP Register Field Descriptions
Bit Field Type Reset Description
31-0 RX_CP R/W 0h Rx Completion Pointer Register - This register is written by the host
with the buffer descriptor address for the last buffer processed by the
host during interrupt processing.
The port uses the value written to determine if the interrupt should
be deasserted.
Note: The value read is the completion pointer (interrupt
acknowledge) value that was written by the CPDMA DMA controller
(port).
The value written to this register by the host is compared with the
value that the port wrote to determine if the interrupt should remain
asserted.
The value written is not actually stored in the location.
The interrupt is deasserted if the two values are equal.
14.5.6 CPSW_PORT Registers
Table 14-135 lists the memory-mapped registers for the CPSW_PORT. All register offset addresses not
listed in Table 14-135 should be considered as reserved locations and the register contents should not be
modified.
Table 14-135. CPSW_PORT REGISTERS
Offset Acronym Register Name Section
0h P0_CONTROL Section 14.5.6.1
8h P0_MAX_BLKS Section 14.5.6.2
Ch P0_BLK_CNT Section 14.5.6.3
10h P0_TX_IN_CTL Section 14.5.6.4
14h P0_PORT_VLAN Section 14.5.6.5
18h P0_TX_PRI_MAP Section 14.5.6.6
1Ch P0_CPDMA_TX_PRI_MAP Section 14.5.6.7
20h P0_CPDMA_RX_CH_MAP Section 14.5.6.8
30h P0_RX_DSCP_PRI_MAP0 Section 14.5.6.9
34h P0_RX_DSCP_PRI_MAP1 Section 14.5.6.10
38h P0_RX_DSCP_PRI_MAP2 Section 14.5.6.11
3Ch P0_RX_DSCP_PRI_MAP3 Section 14.5.6.12
40h P0_RX_DSCP_PRI_MAP4 Section 14.5.6.13
44h P0_RX_DSCP_PRI_MAP5 Section 14.5.6.14
48h P0_RX_DSCP_PRI_MAP6 Section 14.5.6.15
4Ch P0_RX_DSCP_PRI_MAP7 Section 14.5.6.16
100h P1_CONTROL Section 14.5.6.17
108h P1_MAX_BLKS Section 14.5.6.18
10Ch P1_BLK_CNT Section 14.5.6.19
110h P1_TX_IN_CTL Section 14.5.6.20
1355
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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Texas Instruments AM335 Series Specifications

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Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English