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Functional Description
Sleep mode is a good way to lower UART power consumption, but this state can be achieved only when
the UART is set to modem mode. Therefore, even if the UART has no key role functionally, it must be
initialized in a functional mode to take advantage of sleep mode.
In sleep mode, the module clock and baud rate clock are stopped internally. Because most registers are
clocked by these clocks, this greatly reduces power consumption. The module wakes up when a change
is detected on the uarti_rx line, when data is written to the TX FIFO, and when there is a change in the
state of the modem input pins.
An interrupt can be generated on a wake-up event by setting the UARTi.UART_SCR[4] RX_CTS_WU_EN
bit to 1. To understand how to manage the interrupt, see Section 19.3.5.2, Wake-Up Interrupt.
NOTE: There must be no writing to the divisor latches, UARTi.UART_DLL and UARTi.UART_DLH,
to set the baud clock (BCLK) while in sleep mode. It is advisable to disable sleep mode using
the UARTi.UART_IER[4] SLEEP_MODE bit before writing to the UARTi.UART_DLL register
or the UARTi.UART_DLH register.
19.3.4.1.2 System Power Saving
Sleep and auto-idle modes are embedded power-saving features. Power-reduction techniques can be
applied at the system level by shutting down certain internal clock and power domains of the device.
The UART supports an idle req/idle ack handshaking protocol used at the system level to shut down the
UART clocks in a clean and controlled manner and to switch the UART from interrupt-generation mode to
wake-up generation mode for unmasked events (see the UARTi.UART_SYSC[2] ENAWAKEUP bit and
the UARTi.UART_WER register).
For more information, see Module Level Clock Management in Chapter 8, Power, Reset, and Clock
Management.
19.3.4.2 IrDA/CIR Mode Power Management
19.3.4.2.1 Module Power Saving
In IrDA/CIR modes, sleep mode is enabled by setting the UARTi.MDR[3] IR_SLEEP bit to 1.
Sleep mode is entered when all the following conditions exist:
• The serial data input line, uarti.rx_irrx, is idle.
• The TX FIFO and TX shift register are empty.
• The RX FIFO is empty.
• No interrupts are pending except THR interrupts.
The module wakes up when a change is detected on the uarti_rx_irrx line or when data is written to the
TX FIFO.
19.3.4.2.2 System Power Saving
System power saving for the IrDA/CIR mode has the same function as for the UART mode (see
Section 19.3.4.1.2, System Power Saving).
19.3.4.3 Local Power Management
Table 19-10 describes power-management features available for the UART.
NOTE: For information about source clock gating and sleep/wake-up transitions description, see
Module-Level Clock Management in Chapter 8, Power, Reset, and Clock Management.
3455
SPRUH73H–October 2011–Revised April 2013 Universal Asynchronous Receiver/Transmitter (UART)
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