Texas Instruments AM335 Series Technical Reference Manual

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22.4.1.25 Transmitter Global Control Register (XGBLCTL)
Alias of the global control register (GBLCTL). Writing to the transmitter global control register (XGBLCTL)
affects only the transmit bits of GBLCTL (bits 12-8). Reads from XGBLCTL return the value of GBLCTL.
XGBLCTL allows the transmitter to be reset independently from the receiver. The XGBLCTL is shown in
Figure 22-63 and described in Table 22-36. See Section 22.4.1.9 for a detailed description of GBLCTL.
Figure 22-63. Transmitter Global Control Register (XGBLCTL)
31 16
Reserved
R-0
15 13 12 11 10 9 8
Reserved XFRST XSMRST XSRCLR XHCLKRST XCLKRST
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 5 4 3 2 1 0
Reserved RFRST RSMRST RSRCLR RHCLKRST RCLKRST
R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-36. Transmitter Global Control Register (XGBLCTL) Field Descriptions
Bit Field Value Description
31-13 Reserved 0-FFh Reserved. The reserved bit location always returns the default value. A value written to this field has no
effect. If writing to this field, always write the default value for future device compatibility.
12 XFRST Transmit frame sync generator reset enable bit. A write to this bit affects the XFRST bit of GBLCTL.
0 Transmit frame sync generator is reset.
1 Transmit frame sync generator is active.
11 XSMRST Transmit state machine reset enable bit. A write to this bit affects the XSMRST bit of GBLCTL.
0 Transmit state machine is held in reset.
1 Transmit state machine is released from reset.
10 XSRCLR Transmit serializer clear enable bit. A write to this bit affects the XSRCLR bit of GBLCTL.
0 Transmit serializers are cleared.
1 Transmit serializers are active.
9 XHCLKRST Transmit high-frequency clock divider reset enable bit. A write to this bit affects the XHCLKRST bit of
GBLCTL.
0 Transmit high-frequency clock divider is held in reset.
1 Transmit high-frequency clock divider is running.
8 XCLKRST Transmit clock divider reset enable bit. A write to this bit affects the XCLKRST bit of GBLCTL.
0 Transmit clock divider is held in reset.
1 Transmit clock divider is running.
7-5 Reserved 0 Reserved. The reserved bit location always returns the default value. A value written to this field has no
effect. If writing to this field, always write the default value for future device compatibility.
4 RFRST x Receive frame sync generator reset enable bit. A read of this bit returns the RFRST bit value of
GBLCTL. Writes have no effect.
3 RSMRST x Receive state machine reset enable bit. A read of this bit returns the RSMRST bit value of GBLCTL.
Writes have no effect.
2 RSRCLR x Receive serializer clear enable bit. A read of this bit returns the RSRSCLR bit value of GBLCTL. Writes
have no effect.
1 RHCLKRST x Receive high-frequency clock divider reset enable bit. A read of this bit returns the RHCLKRST bit value
of GBLCTL. Writes have no effect.
0 RCLKRST x Receive clock divider reset enable bit. A read of this bit returns the RCLKRST bit value of GBLCTL.
Writes have no effect.
3861
SPRUH73H–October 2011–Revised April 2013 Multichannel Audio Serial Port (McASP)
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Texas Instruments AM335 Series Specifications

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Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English