SPICLK Edge Nr.
Sample
End
Begin
SPICLK (POL=0)
SPICLK (POL=1)
Data From the Master
Data From the Slave
Slave Select
(SPIEN) (optional)
1 2
3
4
5
6
7
8 9 10
11 12
13
14
15 16
MSB
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
LSB
MSB
Bit6
Bit5
Bit4
Bit3
Bit2 Bit1
LSB
t
LEAD
t
LAG
Transfer
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Functional Description
24.3.1.3.8 Transfer Format With PHA = 1
This section describes SPI full duplex transmission with the SPI mode1 and the SPI mode3.
In the transfer format with PHA = 1, SPIEN is activated a delay (t
Lead
) ahead of the first SPICLK edge.
In both master and slave modes, McSPI drives the data lines on the first SPICLK edge.
Each data frame is transmitted starting with the MSB. At the extremity of both SPI data lines, the first bit of
SPI word is valid on the next SPICLK edge, a half-cycle later of SPICLK. It is the sampling edge for both
the master and slave.
When the third edge occurs, the received data bit is shifted into the shift register. The next data bit of the
master is provided to the serial input pin of the slave.
This process continues for a total of pulses on the SPICLK line defined by the word length programmed in
the master device, with data being latched on even numbered edges and shifted on odd numbered edges.
Figure 24-8 is a timing diagram of a SPI transfer for the SPI mode1 and the SPI mode3, when McSPI is
master or slave, with the frequency of SPICLK equals to the frequency of CLKSPIREF. It should not be
used as a replacement for SPI timing information and requirements detailed in the data manual.
The SPIEN line may remain active between successive transfers. In 3-pin mode without using the SPIEN
signal, the controller provides the same waveform but with SPIEN forced to low state. In slave mode
SPIEN is useless.
Figure 24-8. Full Duplex Single Transfer Format With PHA = 1
4003
SPRUH73H–October 2011–Revised April 2013 Multichannel Serial Port Interface (McSPI)
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