DMTimer 1ms
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20.2.5.14 TSICR Register (offset = 40h) [reset = 0h]
TSICR is shown in Figure 20-48 and described in Table 20-49.
Timer Synchronous Interface Control Register
Figure 20-48. TSICR Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved POSTED SFT Reserved
R-0h R/W-0h R/W-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-49. TSICR Register Field Descriptions
Bit Field Type Reset Description
31-3 Reserved R 0h
Reads return 0
2 POSTED R/W 1h
PIFREQRATIO
0x0 = Posted mode inactive: will delay the command accept output
signal. NOTE: This mode is not recommended on this device.
0x1 = Posted mode active (clocks ratio needs to fit freq (timer) less
than freq (OCP)/4 frequency requirement).
1 SFT R/W 0h
This bit reset all the functional part of the module
0 = SFT_0 : software reset is disabled
1 = SFT_1 : software reset is enabled
0 Reserved R 0h
Reads return 0
3614
Timers SPRUH73H–October 2011–Revised April 2013
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