I2C Registers
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21.4 I2C Registers
NOTE: All bits defined as reserved must be written by software with 0s, for preserving future
compatibility. When read, any reserved bit returns 0. Also, note that it is good software
practice to use complete mask patterns for setting or testing individually bit fields within a
register.
21.4.1 I2C Registers
Table 21-8 lists the memory-mapped registers for the I2C. All register offset addresses not listed in
Table 21-8 should be considered as reserved locations and the register contents should not be modified.
Table 21-8. I2C REGISTERS
Offset Acronym Register Name Section
00h I2C_REVNB_LO Section 21.4.1.1
04h I2C_REVNB_HI Section 21.4.1.2
10h I2C_SYSC Section 21.4.1.3
24h I2C_IRQSTATUS_RAW Section 21.4.1.4
28h I2C_IRQSTATUS Section 21.4.1.5
2Ch I2C_IRQENABLE_SET Section 21.4.1.6
30h I2C_IRQENABLE_CLR Section 21.4.1.7
34h I2C_WE Section 21.4.1.8
38h I2C_DMARXENABLE_SET Section 21.4.1.9
3Ch I2C_DMATXENABLE_SET Section 21.4.1.10
40h I2C_DMARXENABLE_CLR Section 21.4.1.11
44h I2C_DMATXENABLE_CLR Section 21.4.1.12
48h I2C_DMARXWAKE_EN Section 21.4.1.13
4Ch I2C_DMATXWAKE_EN Section 21.4.1.14
90h I2C_SYSS Section 21.4.1.15
94h I2C_BUF Section 21.4.1.16
98h I2C_CNT Section 21.4.1.17
9Ch I2C_DATA Section 21.4.1.18
A4h I2C_CON Section 21.4.1.19
A8h I2C_OA Section 21.4.1.20
ACh I2C_SA Section 21.4.1.21
B0h I2C_PSC Section 21.4.1.22
B4h I2C_SCLL Section 21.4.1.23
B8h I2C_SCLH Section 21.4.1.24
BCh I2C_SYSTEST Section 21.4.1.25
C0h I2C_BUFSTAT Section 21.4.1.26
C4h I2C_OA1 Section 21.4.1.27
C8h I2C_OA2 Section 21.4.1.28
CCh I2C_OA3 Section 21.4.1.29
D0h I2C_ACTOA Section 21.4.1.30
D4h I2C_SBLOCK Section 21.4.1.31
3716
I2C SPRUH73H–October 2011–Revised April 2013
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